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This paper describes the noise reduction for fully integrated CMOS PLL. Since the Switching of large digital system introduces power supply or substrate noise which perturb the more sensitive blocks in a PLL. Which work as dominant jitter for VCO. This paper describes designs for both a PLL and a clock buffer that reduce sensitivity to supply noise for low-power applications. The supply noise rejection can be done by using active or passive filter and improving supply sensitivity. We are using both method for reduce noise to improve performance of PLL. By designing of low noise PLL, the high static and dynamic supply noise rejection have been achived. Design uses static CMOS Inverter as a building block of VCO and clocking buffering. The design is fabricated at 0.125 m technology.
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